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QCOTSTM UT8Q512K32 16Megabit SRAM MCM
Data Sheet June, 2003
FEATURES q 25ns maximum (3.3 volt supply) address access time q MCM contains four (4) 512K x 8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24, or 32-bit data width q TTL compatible inputs and output levels, three-state bidirectional data bus q Typical radiation performance - Total dose: 50krads - SEL Immune >80 MeV-cm2 /mg - LET TH(0.25) = >10 MeV-cm 2/mg - Saturated Cross Section cm2 per bit, 5.0E-9 - <1E-8 errors/bit-day, Adams 90% geosynchronous heavy ion q Packaging options: - 68-lead dual cavity ceramic quad flatpack (CQFP) (weight 7.37 grams) q Standard Microcircuit Drawing 5962-01533 - QML T and Q compliant part
INTRODUCTION The QCOTSTM UT8Q512K32 Quantified Commercial Off-the-Shelf product is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a common output enable. Memory expansion is provided by an active LOW chip enable (En), an active LOW output enable (G), and three-state drivers. This device has a powerdown feature that reduces power consumption by more than 90% when deselected. Writing to each memory is accomplished by taking the chip enable (En) input LOW and write enable ( Wn) inputs LOW. Data on the I/O pins is then written into the location specified on the address pins (A0 through A 18 ). Reading from the device is accomplished by taking the chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die.
E3 A(18:0) G
W3
E2
W2
E1
W1
E0
W0
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24) or DQ3(7:0)
DQ(23:16) or DQ2(7:0)
DQ(15:3) or DQ1(7:0)
DQ(7:0) or DQ0(7:0)
Figure 1. UT8Q512K32 SRAM Block Diagram
DEVICE OPERATION Each die in the UT8Q512K32 has three control inputs called Enable (En), Write Enable (Wn), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The device enable (En) controls device selection, active, and standby modes. Asserting En enables the device, causes I DD to rise to its active value, and decodes the 19 address inputs to each memory die by selecting the 2,048,000 byte of memory. Wn controls read and write operations. During a read cycle, G must be asserted to enable the outputs. Table 1. Device Operation Truth Table
NC A0 A1 A2 A3 A4 A5 E2 V SS E3 W0 A6 A7 A8 A9 A10 V DD DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) V SS DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Top View DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) VSS DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3)
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 V DD A11 A12 A13 A14 A15 A16 E0 G E1 A17 W1 W2 W3 A18 NC NC
G X1 X
Wn X 0 1 1
En 1 0 0 0
I/O Mode 3-state Data in 3-state Data out
Mode Standby Write Read2 Read
Figure 2. 25ns SRAM Pinout (68)
1 0
PIN NAMES A(18:0) DQ(7:0) En Address Data Input/Output Device Enable Wn G VDD V SS WriteEnable Output Enable Power Ground
Notes: 1. "X" is defined as a "don't care" condition. 2. Device active; outputs disabled.
READ CYCLE A combination of Wn greater than V IH (min) with En and G less than V IL (max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. SRAM read Cycle 1, the Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and Wn deasserted. Valid data appears on data outputs DQn(7:0) after the specified t AVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t AVAV ). SRAM read Cycle 2, the Chip Enable-controlled Access is initiated by En going active while G remains asserted, Wn remains deasserted, and the addresses remain stable for the entire cycle. After the specified t ETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQn(7:0). SRAM read Cycle 3, the Output Enable-controlled Access is initiated by G going active while En is asserted, Wn is deasserted, and the addresses are stable. Read access time is tGLQV unless t AVQV or tETQV have not been satisfied.
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WRITE CYCLE A combination of Wn less than VIL(max) and En less than VIL(max) defines a write cycle. The state of G is a "don't care" for a write cycle. The outputs are placed in the high-impedance state when eitherG is greater than V IH(min), or when Wn is less than VIL (max). Write Cycle 1, the Write Enable-controlled Access is defined by a write terminated by Wn going high, with En still active. The write pulse width is defined by tWLWH when the write is initiated byWn, and by t ETWH when the write is initiated by En. Unless the outputs have been previously placed in the highimpedance state byG, the user must wait t WLQZ before applying data to the eight bidirectional pins DQn(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable-controlled Access is defined by a write terminated by the former of En or Wn going inactive. The write pulse width is defined by tWLEF when the write is initiated by Wn, and by t ETEF when the write is initiated by the En going active. For the Wn initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQn(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS The UT8Q512K32 SRAM incorporates features which allow operation in a limited radiation environment. Table 2. Typical Radiation Hardness Design Specifications 1 Total Dose Heavy Ion Error Rate 2 50 <1E-8 krad(Si) nominal Errors/Bit-Day
Notes: 1. The SRAM will not latchup during radiation exposure under recommended operating conditions. 2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum.
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ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS ) SYMBOL VDD V I/O TSTG PD TJ JC II PARAMETER DC supply voltage Voltage on any pin Storage temperature Maximum power dissipation Maximum junction temperature 2 Thermal resistance, junction-to-case3 DC input current LIMITS -0.5 to 4.6V -0.5 to 4.6V -65 to +150C 1.0W (per byte) +150C 10C/W
10 mA
Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL VDD TC VIN PARAMETER Positive supply voltage Case temperature range DC input voltage LIMITS 3.0 to 3.6V -40 to +125C 0V to V DD
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DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-40C to +125C) (V DD = 3.3V + 0.3) SYMBOL V IH V IL V OL1 V OL2 VOH1 VOH2 CIN 1 CIO 1 IIN I OZ PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional I/O capacitance Input leakage current Three-state output leakage current (CMOS) (CMOS) IOL = 8mA, V DD =3.0V IOL = 200A,VDD =3.0V IOH = -4mA,VDD =3.0V IOH = -200A,VDD =3.0V = 1MHz @ 0V = 1MHz @ 0V VSS < V IN < V DD, VDD = VDD (max) 0V < VO < V DD VDD = VDD (max) G = V DD (max) IOS 2, 3 IDD (OP) Short-circuit output current Supply current operating @ 1MHz (per byte) 0V < VO < V DD Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) IDD2 (SB) Nominal standby supply current @0MHz (per byte) Inputs: VIL = VSS IOUT = 0mA En = VDD - 0.5, VDD = VDD (max) VIH = V DD - 0.5V
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 101 9 . 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second.
CONDITION
MIN 2.0
MAX
UNIT V
0.8 0.4 0.08 2.4 V DD-0.10 32 16 -2 -2 2 2
V V V V V pF pF A A
-90
90 125
mA mA
I DD1(OP)
Supply current operating @40MHz (per byte)
180
mA
-40C and 25C +125C
6 40
mA mA
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AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-40C to +125C) (V DD = 3.3V + 0.3) SYMBOL tAVAV 1 tAVQV tAXQX 2 tGLQX 2 tGLQV tGHQZ 2 tETQX 2,3 tETQV 3 tEFQZ 1 ,2 ,4 Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle 3) G-controlled output three-state time En-controlled Output Enable time En-controlled access time En-controlled output three-state time 3 25 10 3 3 10 10 PARAMETER MIN 25 25 MAX UNIT ns ns ns ns ns ns ns ns ns
Notes: * Post-radiation performance guaranteed at 25 C per MIL-STD-883 Method 1019. 1. Functional test. 2. Three-state is defined as a 300mV change from steady-state output voltage. 3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters. 4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
High Z to Active Levels
Active to High Z Levels
VLOAD + 300mV } VLOAD VLOAD - 300mV { { }
VH - 300mV
VL + 300mV
Figure 3. 3-Volt SRAM Loading
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tAVAV A(18:0)
DQn(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: 1 . En andG < V IL (max) and Wn > V IH (min)
tAXQX Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0) En t ETQV DQn(7:0) tETQX tEFQZ
DATA VALID
Assumptions: 1. G < V IL (max) and Wn > V IH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
t AVQV A(18:0) G tGHQZ tGLQX DQn(7:0)
Assumptions: 1 . En < VIL (max) andW n > V IH (min)
DATA VALID
tGLQV
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
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AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-40C to +125C) (V DD = 3.3V + 0.3) SYMBOL tAVAV 1 tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ 2 tWHQX2 tETEF tDVWH tWHDX2 tWLEF tDVEF 2 tEFDX tAVWH tWHWL1 Write cycle time Device Enable to end of write Address setup time for write (En - controlled) Address setup time for write (Wn - controlled) Write pulse width Address hold time for write (Wn - controlled) Address hold time for Device Enable (En - controlled) Wn- controlled three-state time Wn - controlled Output Enable time Device Enable pulse width (En - controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid to end of write Write disable time 5 20 15 2 20 15 2 20 5 PARAMETER MIN 25 20 1 0 20 2 2 10 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 101 9 . 1. Functional test performed with outputs disabled (G high). 2. Three-state is defined as 300mV change from steady-state output voltage .
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A(18:0) t AVAV2 En tAVWH t ETWH Wn tAVWL Qn(7:0) tWLQZ Dn(7:0)
Assumptions: 1. G < V IL (max). If G > V IH (min) then Qn(8:0) will be in three-state for the entire cycle. 2. G high for t AVAV cycle. APPLIED DATA
t WHWL tWHAX
t WLWH
tWHQX
tDVWH
tWHDX
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
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tAVAV 3 A(18:0) t AVET tETEF tEFAX En
or
t AVET En tETEF tWLEF
APPLIED DATA
tEFAX
Wn Dn(7:0)
t WLQZ Qn(7:0)
t DVEF
t EFDX
Assumptions & Notes: 1. G < V IL (max). If G > V IH (min) then Qn(7:0) will be in three-state for the entire cycle. 2. Either En scenario above can occur. 3. G high for t AVAV cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
CMOS V DD-0.05V 300 ohms V LOAD = 1.55 10% 0.5V < 5ns 50pF Input Pulses < 5ns 10% 90% 90%
Notes: 1. 50pF including scope probe and test socket capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = V DD/2).
Figure 6. AC Test Loads and Input Waveforms
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DATA RETENTION MODE
VDD
50% t EFR
VDR > 2.0V
50% tR
En
Figure 7. Low V DD Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (1 Second Data Rentention Test) SYMBOL PARAMETER V DR I DDR 1,2 tEFR 1,3 tR1,3 VDD for data retention Data retention current (per byte) Chip select to data retention time Operation recovery time
MINIMUM 2.0 -0 tAVAV
MAXIMUM -2.0
UNIT V mA ns ns
Notes: 1. En = V DD - .2V, all other inputs = V DR or VSS . 2. Data retention current (ID D R) Tc = 25oC. 3. Not guaranteed or tested. 4. VDR = T=-40 oC and 125 oC.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) (10 Second Data Retention Test, TC=-40oC and +125oC) SYMBOL V DD1 tEFR2, 3 tR2, 3 PARAMETER VDD for data retention Chip select to data retention time Operation recovery time MINIMUM 3.0 0 tAVAV MAXIMUM 3.6 UNIT V ns ns
Notes: 1. Performed at VDD (min) and VDD (max). 2. En = V SS, all other inputs = V DR or V SS . 3. Not guaranteed or tested.
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PACKAGING
Notes: 1. Package shipped with non-conductive strip (NCS). Leads are not trimmed. 2. Total weight approx. 7.37g.
Figure 8. 68-pin Ceramic FLATPACK
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ORDERING INFORMATION 512K32 16Megabit SRAM MCM:
UT8Q512K32 -* *
*
*
Lead Finish: (C) = Gold
Screening: (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40 o C to +125o C)
Package Type: (S) = 68-lead dual cavity CQFP
Device Type: - = 25ns access, 3.3V operation Aeroflex UTMC Core Part Number
Notes: 1. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. 2. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows document. Devices are tested at -40 oC to +125 oC. Radiation neither tested nor guaranteed. Gold lead finish only.
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512K32 16Megabit SRAM MCM: SMD
5962 - 01533 **
** *
Lead Finish: (C) = Gold
Case Outline: (X) = 68-lead dual cavity CQFP Class Designator: (T) = QML Class T (Q) = QML Class Q
Device Type 01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40 o C to +125o C)
Drawing Number: 01533 Total Dose (-) = none (D) = 1E4 (10krad(Si)) (L) = 5E4 (50krad(Si)) (contact factory) (P) = 3E4 (30krad(Si)) (contact factory) Federal Stock Class Designator: No Options
Notes: 1. Total dose radiation must be specified when ordering. Gold lead finish only. 2. Only Extended Industrial Temperature -40C to +125C. No military temp. test available.
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